In general, dynamic random access memory (DRAM) devices can be highly integrated and have high operation speed, however, the charge stored in a capacitor of a DRAM cell as data may be lost due to leakage current. Accordingly, to prevent the loss of charge, data refresh operations are typically required. Meanwhile, static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM) and flash memory typically require high operation voltages, typically have relatively low integration capability, and relatively low operation speed. However, a ferroelectric memory (FRAM) device is formed by using the physical characteristics of a ferroelectric material to store data. In the ferroelectric material, electric dipoles are arranged in the direction of an electric field when a voltage of sufficient magnitude (i.e., polarization voltage) is applied. When this occurs, data is retained as residual polarization in the ferroelectric material, even after the polarization voltage has been removed.
Ferroelectric nonvolatile memory devices are largely classified as one of two types. One type detects a change in charge stored in a ferroelectric capacitor, and another type detects a change in resistance in a semiconductor substrate due to the spontaneous polarization of the ferroelectric material. The method for detecting a change in the level of charge stored in a ferroelectric capacitor is adapted to a structure in which a unit cell is formed of one capacitor and one transistor, as a DRAM cell. Unfortunately, data may be lost when the state of the ferroelectric capacitor is read (i.e., a destructive read out occurs). The method for detecting a resistance change in a semiconductor substrate due to spontaneous polarization of a ferroelectric material is typically adapted to a metal ferroelectric metal insulator semiconductor (MFMIS) structure. In the MFMIS structure, a unit cell is typically formed of one transistor. Accordingly, the cell area is smaller than that of a DRAM having a structure of one-transistor and one-capacitor. Also, a long write period is typically not required and a nondestructive read out operation can typically be performed so that data is maintained even after being read. A switching transistor is typically required for operating a ferroelectric memory cell having a one-transistor structure. Therefore, each unit cell of the ferroelectric memory includes a memory cell transistor and a switching transistor.
FIG. 1 is a sectional view of a ferroelectric memory device having a one-transistor structure, as disclosed in U.S. Pat. No. 5,412,596. Referring to FIG. 1, a ferroelectric transistor FT containing a ferroelectric layer 4, a source region 16, a drain region 2, and a first gate region WL2a, is formed on a P-type semiconductor substrate 3. A first interdielectric layer 13 for insulating the first gate electrode WL2a of the ferroelectric transistor FT from a second gate electrode WL1a of a switching transistor ST is formed on the entire surface of the substrate. The switching transistor ST is formed on the first interdielectric layer 13 by sequentially stacking a gate insulating layer 15 and the second gate electrode WL1a. A channel region formed between the drain region 2 and the source region 16 is partially covered by the ferroelectric layer 4, and the rest thereof is covered by the second gate electrode WL1a under which the gate insulating layer 15 is interposed. The first and second gate electrodes are connected to the second and first word lines WL2a and WL1a, respectively. Drain region 2 of the ferroelectric transistor FT (or the switching transistor ST) is connected to a bit line BL, and source region thereof 16 is connected to a source line SL. Unfortunately, the unit memory cell of U.S. Pat. No. 5,412,596 requires both a ferroelectric transistor FT and a switching transistor ST, which means the unit cell size is relatively large and the relatively complicated arrangement of the cell may require complicated processing steps during fabrication.
Thus, notwithstanding the above described ferroelectric memory devices, there continues to be a need for improved ferroelectric-based memory devices that have small unit cell size and can be fabricated using relatively simple processing steps.